Today's processors are broadly divided into a PC/server processor whose performance has been assigned the highest priority, and a built-in processor that requires the compatibility of high efficiency and high performance. As the built-in processor that needs high efficiency, an RISC (Reduced Instruction Set Computer) type built-in processor using a 16-bit fixed-length instruction set, which is capable of realizing high code efficiency, is in widespread use. The high code efficiency is essential to the effective use of an on-chip cache, a RAM and a ROM even at the present time that greater capacitance in an on-chip memory has been advanced. In the 16-bit fixed-length instruction set, however, a program size can be reduced, but on the other hand the number of instructions increases. In particular, the number of register-to-register transfer or immediate transfer instructions increases due to a restriction on operand designation. In order to obscure the latency of the increased transfer instructions, source forwarding for forwarding the value of a transfer source register instead of a transfer destination register has been commonly used. An increase in the number of instructions leads to performance degradation and an increase in electric power. The source forwarding for making up for the performance degradation contributes to a reduction in operating frequency and an increase in power through increases in both the critical path and the logic scale.
Such a problem arises from the fact that instruction code space for the 16-bit fixed-length instruction set is 216B=64 kB, which is much smaller than 232B=4 GB corresponding to instruction code space for a 32-bit fixed-length instruction set. Therefore, in an ARM Thumb-2 instruction set described in, for example, a Non-patent Document 1, a 16-bit fixed-length instruction and a 32-bit fixed-length instruction are allowed to exist in mixed form to thereby expand instruction code space. On the other hand, in a processor described in a Patent Document 1, a 16-bit prefix is added to a 16-bit fixed-length instruction set to thereby expand instruction code space. The prefix described herein is of an instruction code having the function of changing the meaning of an instruction code to be followed up and adding information to the followed-up instruction code. The prefix does not assume an instruction by itself. Incidentally, the prefix was used when the Intel's i386 processor published in 1985, which was used under the 16-bit architecture up to now, is brought to a 32-bit architecture while maintaining upward compatibility, and has been known for more than 20 years. In the i386 processor, the prefix is used to change the meaning of an operand size of the following instruction code. Since the i386 processor and its succeeding models are all CISC (Complicated Instruction Set Computer) type processors each using a variable-length instruction set, it can be said that an instruction decode circuit is originally complicated and the influence thereof on a realization circuit with the addition of the prefix is relatively small.
The prefix described in the Patent Document 1 has been used for a case in which an operand is added to a two-operand instruction to form a three-operand instruction, a case in which an index is added to an instruction of register indirect addressing to make a change to an instruction of register relative indirect addressing, and a case in which a source operand of a two-operand modify type instruction is altered to make a change to a three-operand instruction. The Patent Document 1 has disclosed a realization system with a scalar processor for decoding each instruction code in 16 bits being taken as an example. Since the prefix is also one instruction code, two cycles are required for decoding of a prefixed instruction, and two cycles are required even for its execution.
A processor in which the processor disclosed in the Patent Document 1 has been improved has been disclosed in a Patent Document 2. The Patent Document 2 discloses that as prefix's functions, a destination operand of a two-operand modify type instruction is altered to make a change to a three-operand type, and a bit width of a literal operand is expanded. Of the decoding of the prefixed instruction having required the two cycles in the Patent Document 1, the prefix's decoding is performed simultaneously with a preceding instruction to thereby obscure a prefix's decode cycle and realize one-cycle execution of the prefixed instruction.
As a system for coping with the problem that a register designation field cannot be secured at a 16-bit fixed-length instruction set, there is known an implicit fixed register designation. An SH-4A described in each of Non-patent Documents 2 and 3 defines an instruction under which one register R0 of sixteen general registers is used as an implicit fixed register. In compiler's register allocation, such an implicit fixed register use instruction is assigned R0 on a priority basis. This instruction is utilized to thereby reduce the demerit that the corresponding register is used as the fixed register. However, a reduction in the degree of freedom of a register designation by the fixed operand designation is not necessarily obscured sufficiently. In particular, a compiler's provider for a plurality of processors which intends to handle a variety of instruction set architectures with the same compile system, has a strong tendency not to use the merit of a specific architecture. There is therefore a case in which the utilization of the fixed register use instruction is insufficient. Namely, the fixed register use instruction is not necessarily sufficient as a countermeasure taken against the problem that a register designation field cannot be ensured. It can be said that a further improvement is necessary.    [Patent Document 1] Japanese Patent Laid-Open No. 2000-284962    [Patent Document 2] (Japanese Patent Laid-Open No. 2004-030015)    [Non-patent Document 1] Markus Levy, “ARM Grows More Thumbs,” Microprocessor Report, 6/17/03-02, June 2003.)    [Non-patent Document 2] SH-4A Software Manual, [retrieved on Oct. 19, 2009], Internet URL http://documentation.renesas.com/jpn/products/mpumcu/rjj0 9b0090_sh4a.pdf, p. 3-9˜p. 3-19, Tables 3.4, 3.5, 3.6, 3.9, 3.10 and 3.13    [Non-patent Document 3] SH-4A Software Manual, [retrieved on Oct. 19, 2009], Internet URL http://documentation.renesas.com/eng/products/mpumcu/rej09b0003_sh4a.pdf, pp. 33-42, Tables 3.4, 3.5, 3.6, 3.9, 3.10 and 3.13